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A5973AD
Up to 1.5 A step down switching regulator for automotive applications
Features
Qualified following the AEC-Q100 requirements (temperature grade 3), see PPAP for more details Temperature range -40 C to 85 C 1.5 A DC output current Operating input voltage from 4 V to 36 V 3.3 V / (2 %) reference voltage Output voltage adjustable from 1.235 V to 35 V Low dropout operation: 100 % duty cycle 500 kHz Internally fixed frequency Voltage feedforward Zero load current operation Internal current limiting Inhibit for zero current consumption Synchronization Protection against feedback disconnection Thermal shutdown
HSOP8 exposed pad

Description
The A5973AD is a step down monolithic power switching regulator with a minimum switch current limit of 1.8 A so it is able to deliver more than 1.5 A DC current to the load depending on the application conditions. The output voltage can be set from 1.235 V to 35 V. The high current level is also achieved thanks to an HSOP8 package with exposed frame, that allows to reduce the Rth(JA) down to approximately 40 C/W. The device uses an internal P-channel D-MOS transistor (with a typical RDS(on) of 250 m) as switching element to minimize the size of the external components. An internal oscillator fixes the switching frequency at 500 kHz. Having a minimum input voltage of 4 V only, it is particularly suitable for 5 V bus. Pulse by pulse current limit with the internal frequency modulation offers an effective constant current short circuit protection. Pulse by pulse current limit with the internal frequency modulation offers an effective constant current short circuit protection.
L1 15uH
Applications
Dedicated to automotive applications
Figure 1.
Typical application
VCC COMP
C4
VIN=4V to 35V
8 4 1 2
OUT SYNCH
Vout=3.3V
A5973AD
FB 6 5 7 GND INH 3
D1 STPS340U
R1 5k6 C2 330uF 6.3V R2 3k3
C1 10uF 35V CERAMIC C3 220pF
22nF
R3 4k7
VREF 3.3V
May 2008
Rev 4
1/17
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A5973AD
Contents
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 4
Electical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Oscillator and synchronizator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Additional features and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 5.2 5.3 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 7 8 9
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Pin settings
1
1.1
Pin settings
Pin connection
Figure 2. Pin connection (top view)
1.2
Pin description
Table 1.
N 1
Pin description
Pin OUT Regulator output. Master/slave synchronization. When it is open, a signal synchronous with the turn-off of the internal power is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal. Connecting together the SYNC pin of two devices, the one with the higher frequency works as master and the other one, works as slave. A logical signal (active high) disables the device. With IHN higher than 2.2 V the device is OFF and with INH lower than 0.8 V, the device is ON. If INH is not used the pin must be grounded. When it is open, an internal pullup disables the device. E/A output for frequency compensation. Feedback input. Connecting directly to this pin results in an output voltage of 1.235 V. An extenal resistive divider is required for higher output voltages (the typical value for the resistor connected between this pin and ground is 4.7 k). 3.3 V VREF. No cap is requested for stability. Ground. Unregulated DC input voltage. Description
2
SYNCH
3
INH
4
COMP
5
FB
6 7 8
VREF GND VCC
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Electrical data
2
2.1
Electrical data
Maximum ratings
Table 2.
Symbol V8 V1 I1 V4 , V5 V3 V2 PTOT Tj TSTG Input voltage OUT pin DC voltage OUT pin peak voltage at t = 0.1 s Maximum output current Analog pins INH SYNCH Power dissipation at TA 70 C Operating junction temperature range Storage temperature range
Absolute maximum ratings
Parameter Value 40 -1 to 40 -5 to 40 int. limit. 4 -0.3 to VCC -0.3 to 4 2.25 -40 to 150 -55 to 150 V V V W C C Unit V V V
2.2
Thermal data
Table 3.
Symbol Rth(JA)
Thermal data
Parameter Maximum thermal resistance junction-ambient SO8 40 (1) Unit C/W
1. Package mounted on board
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Electical characteristics
3
Electical characteristics
Table 4. Electrical characteristics (TJ = -40 C to 125 C, VCC = 12 V, unless otherwise specified)
Symbol VCC RDS(on) IL fSW Parameter Operating input voltage range Mosfet on resistance Maximum limiting current Switching frequency Duty cycle Dynamic characteristics (see test circuit). V5 Voltage feedback Efficiency 4.4 V < VCC < 36 V, 20 mA < I0 < 2 A V0 = 5 V, VCC = 12 V 1.198 1.235 90 1.272 V % VCC= 5 V 1.8 430 0 Test condition V0=1.235 V; I0 = 2 A Min 4 0.250 2.3 500 570 100 Typ Max 36 0.5 Unit V A kHz %
DC characteristics Iqop Iq Iqst-by Inhibit Device ON INH threshold voltage Device OFF Error amplifier VOH VOL Io source High level output voltage VFB = 1 V Low level output voltage VFB = 1.5 V Source output current VCOMP = 1.9 V; VFB = 1 V VCOMP = 1.9 V; VFB = 1 V Ib Source bias current DC open loop gain RL = 50 2.5 57 4 A dB 1 1.5 190 300 3.5 0.4 V V A 2.2 V 0.8 V Total operating quiescent current Quiescent current Duty cycle=0;VFB=1.5 V 50 5 7 2.7 100 mA mA A
Total stand-by quiescent Vinh > 2.2 V current
Io sink
Sink output current
mA
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Electical characteristics Table 4. Electrical characteristics (TJ = -40 C to 125 C, VCC = 12 V, unless otherwise specified)
Symbol gm Parameter Transconductance Test condition ICOMP = -0.1 mA to 0.1 mA; VCOMP = 1.9 V Synch function High input voltage Low input voltage Slave synch current VCC= 4.4 to 36 V; VCC= 4.4 to 36 V; Vsynch= 0.74 V (1) Vsynch= 2.33 V Master output amplitude Isource= 3 mA Output pulse width Reference section Reference voltage IREF = 0 to 5 mA VCC = 4.4 V to 36 V Line regulation Load regulation Short circuit current
1. Guaranteed by design.
Min
Typ 2.3
Max
Unit mS
2.5
VREF 0.74
V V mA V s
0.11 0.21 2.75 0.20 3 0.35
0.25 0.45
no load, Vsynch= 1.65 V
3.2
3.3
3.399
V
IREF = 0 mA VCC = 4.4 V to 36 V IREF = 0 mA 10
5 8 18
10 15 30
mV mV mA
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Functional description
4
Functional description
The main internal blocks are shown in Figure 3, where is reported the device block diagram. They are:

A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3 V reference voltage is externally available. A voltage monitor circuit that checks the input and internal voltages. A fully integrated sawtooth oscillator whose frequency is 500 kHz Two embedded current limitations circuitries which control the current that flows through the power switch. The pulse by pulse current limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to strongly reduce the duty cycle. A transconductance error amplifier. A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power. An high side driver for the internal P-MOS switch. An inhibit block for stand-by operation A circuit to realize the thermal protection function. Block diagram

Figure 3.
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Functional description
4.1
Power supply and voltage reference
The internal regulator circuit (shown in Figure 4) consists of a start-up circuit, an internal voltage preregulator, the bandgap voltage reference and the bias block that provides current to all the blocks. The starter gives the start-up currents to the whole device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). The preregulator block supplies the bandgap cell with a preregulated voltage VREG that has a very low supply voltage noise sensitivity.
4.2
Voltages monitor
An internal block senses continuously the VCC, VREF and VBG. If the voltages go higher than their thresholds, the regulator starts to work. There is also an hysteresis on the VCC (UVLO). Figure 4. Internal regulator circuit
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A5973AD
Functional description
4.3
Oscillator and synchronizator
Figure 5 shows the block diagram of the oscillator circuit. The clock generator provides the switching frequency of the device that is internally fixed at 500 kHz. The frequency shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is the input of the Ramp generator and synchronizator blocks. The ramp generator circuit provides the sawtooth signal, used to realize the PWM control and the internal voltage feed forward, while the Synchronizator circuit generates the synchronization signal. Infact the device has a synchronization pin that can works both as master and slave. As master to synchronize external devices to the internal switching frequency. As slave to synchronize itself by external signal. In particular, connecting together two devices, the one with the lower switching frequency works as slave and the other one works as master. To synchronize the device, the SYNC pin has to pass from a low level to a level higher than the synchronization threshold with a duty cycle that can vary approximately from 10 % to 90 %, depending also on the signal frequency and amplitude. The frequency of the synchronization signal must be at least higher than the internal switching frequency of the device (500 kHz). Figure 5. Oscillator circuit
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Functional description
4.4
Current protection
The L5973AD has two current limit protections, pulse by pulse and frequency fold back. The schematic of the current limitation circuitry for the pulse by pulse protection is shown in Figure 3. The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a resistor in series, RSENSE. The current is sensed through Rsense and if reaches the threshold, the mirror is unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the ON time, the output voltage decreases. Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not enough to obtain a sufficiently low duty cycle at 500 kHz, the output current, in strong overcurrent or short circuit conditions, could increase again. For this reason the switching frequency is also reduced, so keeping the inductor current under its maximum threshold. The Frequency Shifter (see Figure 5 on page 9) depends on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases too. Figure 6. Current limitation circuitry
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Functional description
4.5
Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics: Table 5. Uncompensated error amplifier
2300 S 65 dB 1500 A/300 A 0.4 V/3.65 V 2.5 A
Tranconductance Low frequency gain Minimum sink/source voltage Output voltage swing Input bias current
The error amplifier output is compared with the oscillator sawtooth to perform PWM control.
4.6
PWM comparator and power stage
This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM signal for the driving stage. The power stage is a very critical block cause it has to guarantee a correct turn on and turn OFF of the PDMOS. The turn ON of the power element, or better, the rise time of the current at turn on, is a very critical parameter to compromise. At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses. But there is a limit introduced by the recovery time of the recirculation diode. In fact when the current of the power element equals the inductor current, the diode turns off and the drain of the power is free to go high. But during its recovery time, the diode can be considered as an high value capacitor and this produces a very high peak current, responsible of many problems:

Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics. Turn ON overcurrent causing a decrease of the efficiency and system reliability. Big EMI problems. Shorter freewheeling diode life.
The fall time of the current during the turn off is also critical. In fact it produces voltage spikes (due to the parasitics elements of the board) that increase the voltage drop across the PDMOS. In order to minimize all these problems, a new topology of driving circuit has been used and its block diagram is shown in Figure 7 on page 12. The basic idea is to change the current levels used to turn on and off the power switch, according with the PDMOS status and with the gate clamp status. This circuitry allow to turn off and on quickly the power switch and to manage the above question related to the freewheeling diode recovery time problem.
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Functional description The gate clamp is necessary to avoid that Vgs of the internal switch goes higher than Vgsmax. The ON/OFF control block avoids any cross conduction between the supply line and ground. Figure 7. Driving circuitry
4.7
Inhibit function
The inhibit feature allows to put in stand-by mode the device. With INH pin higher than 2.2 V the device is disabled and the power consumption is reduced to less than 100 A. With INH pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also Vcc compatible.
4.8
Thermal shutdown
The shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher than a fixed internal threshold (150 C). The sensing element of the chip is very close to the PDMOS area, so ensuring an accurate and fast temperature detection. An hysteresis of approximately 20 C avoids that the devices turns on and off continuously
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Additional features and protections
5
5.1
Additional features and protections
Feedback disconnection
In case of feedback disconnection, the duty cycle increases versus the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this dangerous condition, the device is turned off if the feedback pin remains floating.
5.2
Output overvoltage protection
The overvoltage protection, OVP, is realized by using an internal comparator, which input is connected to the feedback, that turns off the power stage when the OVP threshold is reached. This threshold is typically 30 % higher than the feedback voltage. When a voltage divider is requested for adjusting the output voltage (see test application circuit), the OVP intervention will be set at: Equation 1
R 1 + R2 V OVP = 1.3 x -------------------- x V FB R2
Where R1 is the resistor connected between the output voltage and the feedback pin, while R2 is between the feedback pin and ground.
5.3
Zero load
Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so, the device works properly also with no load at the output. In this condition it works in burst mode, with random repetition rate of the burst.
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Typical characteristics
6
Typical characteristics
Figure 8. Junction temperature vs output current Figure 9. Junction temperature vs output current
Figure 10. Efficiency vs output current
Figure 11. Efficiency vs output current
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Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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A5973AD Table 6.
Dim Min A A1 A2 b c D D1 E E1 E2 e h L k ccc 0.25 0.40 0.00 1.25 0.31 0.17 4.80 3 5.80 3.80 2.31 4.90 3.1 6.00 3.90 2.41 1.27 0.50 1.27 0.0098 0.0157 0.51 0.25 5.00 3.2 6.20 4.00 2.51 Typ Max 1.70 0.10 0.0492 0.0122 0.0067 0.1890 0.118 0.2283 0.1496 0.091 Min
Package mechanical data HSOP8 mechanical data
mm inch Typ Max 0.0669 0.00 0.0039
0.0201 0.0098 0.1929 0.122 0.1969 0.126 0.2441 0.1575 0.095 0.099
0.0197 0.0500
0 (min), 8 (max) 0.10 0.0039
Figure 12. Package dimensions
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Order codes
8
Order codes
Table 7. Order code
Order code A5973AD HSOP8 A5973ADTR Tape and reel Package Packing Tube
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Revision history
9
Revision history
Table 8.
Date 07-Aug-2007 31-Oct-2007 14-Jan-2008 2-May-2008
Document revision history
Revision 1 2 3 4 Initial release Updated Table 4 on page 5, Table 8 on page 18 Updated Table 6 on page 16 Updated Table 4 on page 5 Changes
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